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? 2012-2014 microchip technology inc. ds20002299c-page 1 mcp2050 features: ? the mcp2050 is compliant with: - lin bus specifications version 1.3, 2.1 and with sae j2602-2 ? support baud rates up to 20 kbaud ? 43v load dump protected ? maximum continuous input voltage of 30v ? wide lin compliant supply voltage, 6.0-18.0v ? extended temperature range: -40 to +125c ? interface to pic ? eusart and standard usarts ? wake-up on lin bus activity or local wake input ? lin bus pin - internal pull-up termination resistor and diode for slave node - protected against v bat shorts - protected against loss of ground - high current drive ?t xd and lin bus dominant time-out function ? two low-power modes - transmitter off mode: 90 a (typical) - power down mode: 4.5 a (typical) ? output indicating internal reset state (por or sleep wake) ? mcp2050 on-chip voltage regulator - output voltage of 5.0v or 3.3v with 70 ma capability and tolerances of 3% over operating temperature range - internal short-circuit current limit - only external filter and load capacitors needed ? programmable windowed watchdog timer (wwdt) - external resistor programmable from 7 ms to 140 ms - disabled by connecting the wwdtselect pin to v reg or let the pin float ? ratiometric output of v bat voltage scaled to v reg ? automatic thermal shutdown ? high electromagnetic immunity (emi), low electromagnetic emission (eme) ? robust esd performance: 15 kv for l bus and v bb pin (iec61000-4-2) ? transient protection for l bus and v bb pins in automotive environment (iso7637) ? meets stringent automotive design requirements including ?oem hardware requirements for lin, can and flexray interfaces in automotive applications?, version 1.3, may 2012 ? multiple package options including small 5x5 qfn description: the mcp2050 provides a bidirectional, half-duplex communication physical interface to meet the lin bus specification revision 2.1 and sae j2602. the device incorporates a voltage regulator with 5v or 3.3v 70 ma regulated power supply output. the on-chip wwdt allows users to adjust the size of the reset window by using an external resistor. the ratiometric v bat pin scales down v bat to the range of v reg so it can be monitored by an a/d converter. the device has been designed to meet the stringent quiescent current requirements of the automotive industry and will survive +4 3 v load dump transients, and double battery jumps. mcp2050 family members: - mcp2050-500, 14-pin, lin driver with 5.0v regulator - mcp2050-330, 14-pin, lin driver with 3.3v regulator - mcp2050-500, 20-pin qfn, lin driver with 5.0v regulator - mcp2050-330, 20-pin qfn, lin driver with 3.3v regulator lin transceiver with voltage regulator
mcp2050 ds20002299c-page 2 ? 2012-2014 microchip technology inc. package types block diagram 16 15 14 1 2 3 4 6 7 8 13 12 11 10 9 5 wwdttrig fault /t xe v bb nc v bat ratio wwdtreset nc cs/lwake v reg t xd rxd reset nc v ss l bus 17 18 19 20 nc nc nc nc wwdtselect mcp2050 pdip, soic mcp2050 5x5qfn* ep 21 v bat ratio r xd cs/lwake v reg reset nc wwdtreset wwdttrig wwdtselect fault/t xe v bb l bus v ss 1 2 3 4 14 13 12 11 10 9 8 5 6 7 t xd * includes exposed thermal pad (ep), see tab le 1 - 2 . voltage regulator ratiometric reference thermal protection internal circuits v reg fault/ txe r xd t xd v bb l bus v ss ~30 cs/lwake wake-up logic and power control reset short-circuit protection thermal protection programmable windowed watchdog wwdtreset wwdttrig wwdtselect v bb v reg v bat ratio k ? 4.2v bus wakeup and short-circuit slope control v reg 4.2v bus dominant timer 300 ? v reg
? 2012-2014 microchip technology inc. ds20002299c-page 3 mcp2050 1.0 function description the mcp2050 provides a physical interface between a microcontroller and a lin half-duplex bus. it is intended for automotive and industrial applications with serial bus baud rates up to 20 kbaud. this device will translate the cmos/ttl logic levels to lin logic levels, and vice versa. the device offers optimum emi and esd performance; it can withstand high voltage on the lin bus. the device supports two low-power modes to meet automotive industry power consumption requirements. the mcp2050 also provides a +5v or 3.3v 70 ma regulated power output. 1.1 modes of operation the mcp2050 works in five modes: power-on reset mode, power-down mode, ready mode, operation mode, and transmitter off mode. for an overview of all operational modes, please refer to ta b l e 1 - 1 . for the operational mode transition, please refer to figure 1-1 . figure 1-1: state diagram por ( 2 ) v reg off rx off tx off ready v reg on rx on tx off tx off v reg on rx on tx off power-down v reg off rx off tx off operation v reg on r x on t x on v bb >v on cs/lwake = 1& fault/txe = 0 cs/lwake = 0 cs/lwake = 1& fault/t xe = 1 ( 3 ) & t xd = 1& v reg _ok = 1 ( 1 ) cs/lwake = 1& fault/t xe = 1 (3) & t xd = 1 cs/lwake = 1& fault/t xe = 0 cs/lwake = 0 cs/lwake = 1or voltage rising edge on lbus note 1 vreg_ok: regulator output voltage > 0.8v reg_nom. 2: if the voltage on pin v bb falls below v off , the device will enter power-on reset mode from all other modes, which is not shown in the figure. 3: fault /t xe = 1 represents input and no fault conditions. fault /t xe = 0 represents input low or a fault condition. refer to table 1-3 .
mcp2050 ds20002299c-page 4 ? 2012-2014 microchip technology inc. 1.1.1 power-on-reset mode upon application of v bb , or whenever the voltage on v bb is below the threshold of regulator turn-off voltage v off (typically. 4.50v), the device enters power-on reset mode (por). during this mode, the device maintains the digital section in a reset mode and waits until the voltage on pin v bb rises above the threshold of regulator turn-on voltage v on (typically 5.75v) to enter into ready mode. in power-on-reset mode, the lin physical layer and voltage regulator are disabled, and reset output is forced to low. 1.1.2 ready mode the device enters ready mode from por mode after the voltage on v bb rises above the threshold of regulator turn-on voltage v on or from power-down mode when a remote or local wake-up event happens. upon entering ready mode, the voltage regulator and receiver section of the transceiver are powered up. the transmitter remains in off state. the device is ready to receive data but not to transmit. in order to minimize the power consumption, the regulator operates in a reduced-power mode. it has a lower gbw product and thus is slower. however, the 70 ma drive capability is unchanged. the device stays in ready mode until the output of the voltage regulator has stabilized and the cs/lwake pin is high (? 1 ?). 1.1.3 operation mode if v reg is ok ( v reg > 0.8 v reg _ nom ) , cs/lwake pin, fault /t xe pin and t xd pin are high, the part enters the operation mode from either ready or transmitter off mode . in this mode, all internal modules are operational. the internal pull-up resistor between l bus and v bb is connected only in this mode. the device goes into the power-down mode at the fall- ing edge on cs/lwake; or to the transmitter off mode at the falling on fault /t xe while cs/lwake stays high. 1.1.4 transmitter off mode in transmitter off mode, the receiver is enabled but the l bus transmitter is off. it is a lower-power mode. in order to minimize the power consumption, the window watchdog timer is disabled and the regulator operates in a reduced-power mode. it has a lower gbw product and thus is slower. however, the 70 ma drive capability is unchanged. the transmitter may be re-enabled whenever the fault /t xe signal returns high, by removing the internal fault condition and the cpu returning the fault /t xe high. the transmitter will not be enabled even if the fault /t xe pin is brought high externally, when the internal fault is still present. however, externally forcing the fault/t xe high, while the internal fault is still present, should be avoided since this will induce high current and power dissipation in the fault /t xe pin. the transmitter is also turned off whenever the voltage regulator is unstable or recovering from a fault. this prevents unwanted disruption of the bus during times of uncertain operation. 1.1.5 power-down mode in power-down mode, the transceiver and the voltage regulator are both off. only the bus wake-up section and the cs/lwake pin wake-up circuits are in opera- tion. this is the lowest-power mode. if any bus activity (e.g. a break character) occurs during power-down mode, the device will immediately enter ready mode and enable the voltage regulator. then, once the regulator output has stabilized (approx- imately 0.3 ms to 1.2 ms) it goes to operation mode. refer to section 1.1.6 ?remote wake-up? for more details. the part will also enter ready mode from power-down mode, followed by operation mode, if the cs/lwake pin becomes active high (? 1 ?). 1.1.6 remote wake-up the remote wake-up sub module observes the l bus in order to detect bus activity. in power-down mode, nor- mal lin recessive/dominant threshold is disabled, and the lin bus wake-up voltage threshold v wk(lbus) is used to detect bus activities. bus activity is detected when the voltage on the l bus falls below the lin bus wake-up voltage threshold v wk(lbus) (approximately 3.4v) for at least t bdb (a typical duration of 80 s) fol- lowed by a rising edge. such a condition causes the device to leave power-down mode
? 2012-2014 microchip technology inc. ds20002299c-page 5 mcp2050 . 1.2 windowed watchdog reset the watchdog timer monitors for activity on the windowed watchdog timer trigger input pin wwdttrig . the wwdttrig pin is expected to be strobed within a given time frame. when this time frame has expired without an edge transition on the wwdttrig pin, the wwdtreset pin is driven active (low) to reset the system. this feature is enabled by connecting a resistor between the wwdtselect pin and v ss . monitoring is then done by requiring the host processor to force a falling edge transition on the wwdttrig pin within a predetermined time frame (t wd ). the start time of the trigger window is fixed at 50% of the total watchdog period, after the last trigger. the length of the window is determined by the value of the resistor on pin wwdtselect. the watchdog timer is disabled if wwdtselect is floating. 1.2.1 wwdt during initial power-up the wwdtreset is driven high after a power-on reset. the watchdog timer begins counting at this point, awaiting an edge on wwdttrig pin. note that there is no window enabled, yet. if no falling edge is detected on the wwdttrig pin before the timer expires, the wwdtreset is pulse low and the timer is restarted. when a trigger edge on the wwdttrig pin is seen, the window is enabled and the timer is reset. figure 1-2: wwdtreset during initial power-up figure 1-2 shows the behavior of the wwdtreset pin after a system reset with no trig at all. if no trig is given during the power-up window, wwdtreset is reset low for the time t wdrst . the power-up window length t powerup duration is determined by the value of the resistor connected between pin wwdtselect and pin v ss , while the reset pulse duration is about 150 s. duration for t powerup and t wdrst are: ?t powerup = 0.8 ms x (r wwdtselect +1) typical ?t wdrst = 150 s typical ?r wwdtselect is in k ? ? once a trig is asserted, the power-up sequence ?stops? and the normal behavior begins. table 1-1: overview of operational modes state transmitter receiver internal wake module voltage regulator watch dog timer operation comments por off off off off off proceed to ready mode after v bb >v on .? ready off on off on on if cs/lwake high, then proceed to operation or transmitter off mode. bus off state operation on on off on on if cs/lwake low level, then proceed to power-down. if fault /t xe low level, then transmitter-off mode. normal operation mode power-down off off on activity detect off off on lin bus rising edge or cs/lwake high level, proceed to ready mode. lowest- power mode transmitter off off on off on off if cs/lwake low level, then proceed to power down. if fault /t xe high, then operation mode. bus off state, lower-power mode t powerup t wdrst t powerup internal reset wwdtreset t powerup t wdrst
mcp2050 ds20002299c-page 6 ? 2012-2014 microchip technology inc. 1.2.2 windowed watchdog behavior after windowed watchdog begins its normal behavior, three different cases can appear. ? a pulse (falling edge) on the wwdttrig pin is detected within the trigger window; the watchdog timer will be reset, and a new watchdog period will begin; wwdtreset pin remains high ( figure 1-3 .) ? a pulse (falling edge) on the wwdttrig pin is detected before the trigger window (too early trig- ger); wwdtreset is asserted (low) immediately after the falling edge is detected for approximately t wdrst ; the counter is reset and the next watchdog period begins at the rising edge of the voltage on wwdtreset pin ( figure 1-12 ). ? no pulse on the wwdttrig pin is detected during the whole watchdog window (no trigger); w wdtreset is asserted (low) for approximately t wdrst when the timer has expired; the counter is reset and the next watchdog period begins at the rising edge of the voltage on wwdtreset pin ( figure 1-5 ). the trigger window is between 50% to 100% of the watchdog window length, t wlength . the window length is determined by the external resistor between wwdtselect pin and v ss . equation 1-1: t wdrst = 150 s typical r wwdtselect is in k ? ; its value ranges from 33 k ? to 680 k ? and window length ranges from 7 ms to 120 ms typical. if the wwdtselect pin is floating, the watchdog is disabled and the wwdtreset remains high. figure 1-3: correct trigger t wlength = (0.175 ms rwwdtselect) + 1.2 typical too early trigger window window length 50% earliest trigger point lastest trigger point next period too early trigger window window length 50% new period begins wwdttrig wwdtreset 1 0 1 t wd
? 2012-2014 microchip technology inc. ds20002299c-page 7 mcp2050 figure 1-4: too early trigger figure 1-5: no trigger too early trigger window window length 50% earliest trigger point lastest trigger point next period too early trigger window window length 50% new period begins wwdttrig wwdtreset 1 0 1 0 t wd t wdrst too early trigger window window length 50% earliest trigger point lastest trigger point next period too early trigger window window length 50% new period begins wwdttrig wwdtrese t 1 0 1 t wd no trigger, timer expired t wdrst
mcp2050 ds20002299c-page 8 ? 2012-2014 microchip technology inc. 1.3 pin descriptions please refer to ta b l e 1 - 2 for the pinout overview. table 1-2: pinout descriptions 1.3.1 v bat ratio this is an analog output pin that reflects the voltage at the v bat pin. it is scaled by v reg such that: v bat ratio = v bat /24 v reg 0 <= v bat ratio <= v reg the resistive divider and the output driver are switched off during power-down mode in order to reduce power consumption. 1.3.2 r xd receive data output pin. the r xd pin is a standard cmos output pin and it follows the state of the lbus pin. 1.3.3 cs/lwake chip select and local wake-up input pin (ttl level, high voltage tolerant). this pin controls the device state transition. refer to figure 1-1 . if cs/lwake = 1 , the device can work in operation mode (fault /t xe = 1 ) or transmitter off mode (fault /t xe = 0 ). if cs/lwake = 0 , the device can work in power-down mode or ready mode. an internal pull-down resistor will keep the cs/lwake pin low to ensure that no disruptive data will be present on the bus while the microcontroller is executing a power-on reset and i/o initialization sequence. when cs/lwake is ? 1 ?, a weak pull-down (~600 k ? ) is used to reduce current. when cs/lwake is ? 0 ? a stronger pull-down (~300 k ? ) is used to maintain the logic level. this pin may also be used as a local wake-up input (see figure 1-12 ). the microcontroller will set the i/o pin to control the cs/lwake. an external switch, or other source, can then wake-up both the transceiver and the microcontroller. pin name devices pin type function 14-pin pdip, soic 5 x 5 qfn normal operation v bat ratio 1 18 analog output v bat ratio = v bat /24 v reg r xd 2 1 output receive data output cs/lwake 3 2 ttl input, hv-tolerant chip select and local wake-up input v reg 4 3 output voltage regulator output t xd 5 4 input, hv-tolerant transmit data input reset 6 5 output reset output nc 7 6,9,10,11, 16,19,20 not connected ? v ss 8 8 power ground l bus 97 i/o, hvlin bus v bb 10 12 power battery fault /t xe 11 13 i/o, hv-tolerant fault detect output/transmitter enable input wwdtselect 12 14 input a resistor between this pin and ground determines the watchdog window length wwdttrig 13 15 input windowed watchdog trigger input wwdtreset 14 17 output, hv-tolerant windowed watchdog reset output ep ? 21 exposed thermal pad (ep) exposed thermal pad can be left unconnected, or connected to the ground. note: cs/lwake should not be tied directly to pin v reg as this could force the mcp2050 into operation mode before the microcontroller is initialized.
? 2012-2014 microchip technology inc. ds20002299c-page 9 mcp2050 1.3.4 v reg positive supply voltage regulator output pin. an on- chip ldo gives +5.0 or +3.3v 70 ma regulated voltage on this pin. 1.3.5 t xd transmit data input pin (ttl level, hv compliant, adaptive pull-up). the transmitter reads the data stream on t xd pin and sends it to lin bus. the lbus pin is low (dominant) when t xd is low, and high (recessive) when t xd is high. the transmit data input pin has an internal adaptive pull-up to an internally-generated 4.2v (approximate). when t xd is ? 0 ?, a weak pull-up (~900 k ? ) is used to reduce current. when t xd is ? 1 ? a stronger pull-up (~300 k ? ) is used to maintain the logic level. a series reverse-blocking diode allows applying t xd input voltages greater than the internally generated 4.2v and renders t xd pin hv compliant up to 30v (see the block diagram on page 2). 1.3.6 reset reset output pin. this pin is open drain with ~90 k ? pull-up to v reg . it indicates the internal voltage has reached a valid, stable level. as long as the internal voltage is valid (above 0.8v reg ), this pin will remain high (? 1 ?); otherwise the reset pin switches to low (? 0 ?). 1.3.7 v ss ground pin. 1.3.8 l bus l bus is a bidirectional lin bus interface pin and is controlled by the signal t xd . it has an open collector output with a current limitation. to reduce electromagnetic emission, the slopes during signal changes are controlled, and the l bus pin has corner-rounding control for both falling and rising edges. the internal lin receiver observes the activities on lin bus, and generates the output signal r xd that follows the state of the l bus . a first degree 160 khz, low-pass input filter optimizes electromagnetic immunity. 1.3.9 v bb battery positive supply voltage pin. an external diode is connected in series to prevent the device from being reversely powered (refer figure 1-12 ). 1.3.10 fault /txe fault detect output/transmitter enable input pin. the output section is hv tolerant open drain (up to 30v). the input section is identical with t xd section (ttl level, hv compliant, adaptive pull-up). the internal pull- up resistor may be too weak for some applications. an external 10k ? pull-up resistor is recommended to ensure a logic high level. its state is defined as shown in ta b l e 1 - 3 . the device is placed in transmitter off mode whenever this pin is low (? 0 ?), either from an internal fault condition or by external drive. if cs/lwake is high (? 1 ?), the fault /t xe signals a mis- match between the t xd input and the l bus level. this can be used to detect a bus contention. since the bus exhibits a propagation delay, the sampling of the inter- nal compare is debounced to eliminate false faults. after the device wakes up, the fault /t xe indicates what wakes the device if cs/lwake remains low (? 0 ?) (refer to table 1-3 ). the fault /t xe pin sampled at a rate faster than every 10 s. 1.3.11 wwdtselect this is an analog input pin that sets the open window time to accept a trigger reset. a resistor between this pin and v ss sets this time. the equation to determine the value of the resistor can be found in section 1.2.2 ?windowed watchdog behavior? . 1.3.12 wwdttrig this is an input pin to reset the windowed watchdog timer. a high-to-low transition during the open window time will reset the timer and prevent the wwdt from timing out. the pin has an internal adaptive pull-up to an internally-generated 4.2v (approximate.). when wwdttrig is ? 0 ?, a weak pull-up (~800 k ? ?? is connected ? to reduce current. when wwdttrig is ? 1 ?, the pull-up is stronger to maintain the logic level. 1.3.13 w wdtreset wwdtreset is an open-drain output pin. this pin is asserted low when the internal windowed watchdog timer has expired or an attempt was made to clear the timer before the window has opened. 1.3.14 ep it is recommended to connect this pad to v ss to enhance electromagnetic immunity and thermal resistance.
mcp2050 ds20002299c-page 10 ? 2012-2014 microchip technology inc. figure 1-6: v bat ratio output range table 1-3: fault/ txe truth table t xd in r xd out lin bus i/o thermal override fault/ t xe definition external input driven output cs = 1 lhv bb off h l fault , t xd driven low, l bus shorted to v bb (note 1) , or l bus /t xd permanent dominant detected, and transmit time-out shutdown. hh v bb off h h ok llgnd off h h ok hlgnd off h h ok , data is being received from l bus xxv bb on h l fault , transceiver in thermal shutdown xxv bb xlx no fault , the cpu is commanding the transceiver to turn off the transmitter driver cs = 0 after a wake-up xx x x x l wake-up from lin bus activity xx x x x h wake-up from por legend: x = don?t care note 1: the fault /t xe is valid after approximately 25 s after t xd falling edge. this is to eliminate false fault reporting during bus propagation delays. note 1: linear range of v bat ratio is between v bb = 6.0-18.0v. 0 v bb .25v reg .75v reg v reg /2 v bat ratio 6v 12v 18v 24v
? 2012-2014 microchip technology inc. ds20002299c-page 11 mcp2050 1.4 fail-safe features 1.4.1 general fail-safe features ? an internal pull-down resistor on the cs/lwake pin disables the transmitter if the pin is floating. ? an internal pull-up resistor on the t xd pin places t xd in high, thus the l bus is recessive if the t xd pin is floating. ? high-impedance and low leakage current on l bus during loss of power or ground. ? the current limit on l bus protects the transceiver from being damaged if the pin is shorted to v bb . 1.4.2 thermal protection the thermal protection circuit monitors the die temperature and is able to shut down the lin transmitter and voltage regulator. there are three causes for a thermal overload. a thermal shut down can be triggered by any one, or a combination of, the following thermal overload conditions. ? voltage regulator overload ? lin bus output overload ? increase in die temperature due to increase in environment temperature the recovery time from the thermal shutdown is equal to adequate cooling time. driving the t xd and checking the r xd pin makes it possible to determine whether there is a bus contention (t xd = high, r xd = low) or a thermal overload condition (t xd = low, r xd = high). figure 1-7: thermal shutdown state diagrams 1.4.3 t xd /lbus time-out timer lin bus can be driven to a dominant level either from t xd pin or externally. an internal timer deactivates the l bus transmitter if a dominant status (low) on lin bus lasts longer than bus dominant time-out time t to ( lin ) (approximately 20 ms); at the same time, r xd output is put in recessive (high), fault /t xe is also driven to low and the internal lin pull-up resistor is disconnected. the timer is reset on any recessive l bus status or por mode. the recessive status on l bus can be caused either by the bus being externally pulled up or by t xd pin being returned high. operation mode transmitter shutdown lin bus voltage shutdown regulator output te m p < shutdown temp shorted to v bb overload temp < shutdown temp
mcp2050 ds20002299c-page 12 ? 2012-2014 microchip technology inc. 1.5 internal voltage regulator the mcp2050 has a positive regulator capable of supplying +5.0v or +3.3v at up to 70 ma of load current with tolerances of 3% over the entire operating temperature range of -40c to +125c. the regulator uses an ldo design, is short-circuit-protected and will turn the regulator output off if its output falls below the shutdown voltage threshold v sd . with a load current of 70 ma, the minimum input-to- output voltage differential required for the output to remain in regulation is typically +0.5v (+1v maximum over the full operating temperature range). quiescent current is less than 100 a with a full 70 ma load current when the input-to-output voltage differential is greater than +3.00v. regarding the correlation between v bb , v reg and i dd , refer to figure 1-9 and figure 1-10 . when the input voltage (v bb ) drops below the differential needed to provide stable regulation, the voltage regulator output v reg will track the input down to approximately v off . the regulator will turn off the output at this point. this will allow pic ? microcontrollers, with internal por circuits, to generate a clean arming of the power-on reset trip point. the mcp2050 will then monitor v bb and turn on the regulator when v bb is above the threshold of regulator turn-on voltage v on . under specific ambient temperature and battery voltage range, the voltage regulator can output as high as 150 ma current. for current load capability of the voltage regulator, refer to figure 1-9 and figure 1-10 . in power-down mode, the v bb monitor is turned off. the regulator requires an external output bypass capacitor for stability. see figure 2-1 for correct capacity and esr for stable operation. figure 1-8: voltage regulator block diagram note: the regulator overload current limit is approximately 250 ma. the regulator output voltage v reg is monitored. if output voltage v reg is lower than v sd , the voltage regulator will turn off. after a recovery time of about 3 ms, the v reg will be checked again. if there is no short circuit, (v reg > v sd ) then the voltage regulator remains on. note: a ceramic capacitor of at least 10 f, or a tantalum capacitor of at least 2.2 f is recommended for stability. warning: in worst-case scenarios, the ceramic capacitor may derate by 50%, based on tolerance, voltage and temperature. therefore, in order to ensure stability, ceramic capacitors smaller than 10 f may require a small series resistance to meet the esr requirements, as shown in table 1-4 . table 1-4: recommended series resistance for ceramic capacitors resistance capacitor 1 ? 1f 0.47 ? 2.2 f 0.22 ? 4.7 f 0.1 ? 6.8 f pass element sampling network buffer v reg v bb v ss fast transient loop v ref
? 2012-2014 microchip technology inc. ds20002299c-page 13 mcp2050 figure 1-9: voltage regulator output on power-on reset note 1: start-up, v bb < v on , regulator off. 2: v bb > v on , regulator on. 3: v bb ?? 4: v bb < v off , regulator will turn off. 5 3 2 0 (1) (2) (3) t 0 t 6 2 8 4 v bb v v reg v 1 4 v on v off minimum v bb to maintain regulation v reg-nom minimum v bb to maintain regulation. (4)
mcp2050 ds20002299c-page 14 ? 2012-2014 microchip technology inc. figure 1-10: voltage regulator output on over current situation 1.6 optional external protection 1.6.1 reverse battery protection an external reverse-battery-blocking diode should be used to provide polarity protection (see figure 1-12 ). 1.6.2 transient voltage protection (load dump) an external 43v transient suppressor (tvs) diode, between v bb and ground, with a transient protection resistor (r tp ) in series with the battery supply and the v bb pin protects the device from power transients and esd events greater than 43v (see figure 1-12 ). the maximum value for the r tp protection resistor depends on two parameters: the minimum voltage the part will start at, and the impacts of this r tp resistor on the v bb value, thus on the bus recessive level and slopes. this leads to a set of three equations to fulfill. equation 1-2 provides a max r tp value according to the minimum battery voltage the user wants the part to start at. equation 1-3 provides a max r tp value according to the maximum error on the recessive level thus v bb since the part uses v bb as the reference value for the recessive level. equation 1-4 provides a max r tp value according to the maximum relative variation the user can accept on the slope when i reg varies. since both equation 1-2 and equation 1-3 must be fulfilled, the maximum allowed value for rtp is thus the smaller of the two values found when solving equation 1-2 and equation 1-3 . usually equation 1-2 gives the higher constraint (smaller value) for r tp as shown in the following example where v batmin is 8v. however, the user needs to check that the value found with equation 1-2 also fulfills equation 1-3 and equation 1-4 . while this protection is optional, it should be considered as good engineering practice. note 1: i reg less than l lim , regulator on. 2: after i reg exceeds l lim , the voltage regulator output will be reduced until v sd is reached. v sd 0 (1) (2) t 0 t l lim i reg ma v reg v v reg - nom 1 2 3 4 5 6
? 2012-2014 microchip technology inc. ds20002299c-page 15 mcp2050 equation 1-2: assume v batmin = 8v. equation 1-2 shows 10 ? ? equation 1-3: assume ? v reccessive = 1v and i regmax = 50 ma equation 1-3 shows 20 ? ? equation 1-4: assume ? slope = 15%, v batmin = 8v and i regmax = 50 ma. equation 1-3 shows 20 ? ? 1.6.3 c bat capacitor selecting c bat =10xc reg is recommended. however, this leads to a high-value capacitor. lower values for c bat capacitor can be used with respect to some rules. in any case, the voltage at the v bb pin should remain above v off when the device is turned on. the current peak at start-up (due to the fast charge of the c reg and c bat capacitors) may induce a significant drop on the v bb pin. this drop is proportional to the impedance of the v bat connection (see figure 1-12 ). the v bat connection is mainly inductive and resistive. therefore, it can be modeled as a resistor (r tot ) in series with an inductor (l). r tot and l can be measured. the following formula gives an indication of the minimum value of c bat using r tot and l: equation 1-5: equation 1-5 allows lower c bat /c reg values than the 10x ratio we recommend. assume that we have a good quality v bat connection with r tot =0.1 ? and l = 0.1 mh. solving the equation gives c bat /c reg =1. if we increase r tot up to 1 ?? the result becomes c bat /c reg = 1.4. however, if the connection is highly resistive or highly inductive (poor connection), the c bat /c reg ratio greatly increases. figure 1-11 shows the minimum recommended c bat /c reg ratio as a function of the impedance of the v bat connection. figure 1-11: minimum recommended c bat /c reg ratio 250 ma is the peak current at power-on when v bb =5.5v r tp v batmin 5.5v ? 250ma ------------------------------------ - ? 5.5v v off 1.0v + = r tp v recessive ? i regmax --------------------------------- - ? where: ? v recessive = maximum variation tolerated on the recessive level r tp slope ? v batmin 1v ? ?? ? i regmax ---------------------------------------------------------------- - ? where: ? slope = maximum variation tolerated on the slope level i regmax = maximum current the current will provide to the load v batmin >v off +1.0v table 1-5: c bat /c reg ratio by v bat connection type connection type r tot l c bat /c reg ratio good 0.1 ? 0.1 mh 1 typical 1 ? 0.1 mh 1.4 highly inductive 0.1 ? 1mh 7 highly resistive 10 ? 0.1 mh 7 c bat c reg ------------- - 100l 2 r tot 2 + 1l 2 r tot 2 100 ------------ - ++ ------------------------------------ = where: l = inductor (measured in mh) r tot =r line +r tp (measured in ? ) 1 10 0.1 1 c bat /c reg v bat line inductance [mh] c bat /c reg ratio as function of the v bat line impedance r bat = 10 r bat = 4 r bat = 2 r bat = 1 r bat = 0.3 r bat = 0.1
mcp2050 ds20002299c-page 16 ? 2012-2014 microchip technology inc. 1.7 typical applications figure 1-12: typical application circuit note 1: c reg , the load capacitor, should be ceramic or tantalum rated for extended temperatures, 1.0-22 f. see figure 2-1 for selecting the correct esr. 2: c bat is the filter capacitor for the external voltage supply. it?s typically 10 c reg , with no esr restriction. see figure 1-11 to select the minimum recommended value for c bat . the r tp value is added to the line resistance. 3: this diode is only needed if cs/lwake is connected to v bat supply. 4: esd protection diode. 5: this component is for additional load dump protection. 6: an external 10 k ? resistor is recommended for some applications. lin bus v bb l bus v reg t xd r xd v ss v dd t xd r xd mcu v bat c bat c reg cs/lwake i/o fault/ t xe i/o 43v ( 5 ) 1k ? v bb master node only v bat 220 k ? wake-up ( 3 ) r tp reset reset v ss i/o a/d vbatratio wwdttrig wwdtreset irq wwdtselect 100 nf ( 6 ) ( 6 ) 220 pf mmbz27v ( 4 )
? 2012-2014 microchip technology inc. ds20002299c-page 17 mcp2050 figure 1-13: typical li n network configuration 1.8 icsp? considerations the following should be considered when the mcp2050 is connected to pins supporting in-circuit programming: ? power used for programming the microcontroller can be supplied from the programmer, or from the mcp2050. ? the voltage on the v reg pin should not exceed the maximum value of v reg as shown in section 2.3, dc specifications . lin bus mcp2050 master (mcu) 1k ? v bb slave 1 (mcu) slave 2 (mcu) slave n <16 (mcu) 40m + return lin bus lin bus mcp2050 lin bus mcp202xa lin bus mcp2003
mcp2050 ds20002299c-page 18 ? 2012-2014 microchip technology inc. 2.0 electrical characteristics 2.1 absolute maximum ratings? v in dc voltage on r xd , and reset ................................................................................................ -0.3v to v reg + 0.3 v in dc voltage on t xd , cs/lwake, f ault /t xe ......................................................................................... -0.3 to + 40v v bb battery voltage, continuous, non-operating ( note 1 )............................................................................ -0.3 to + 40v v bb battery voltage, non-operating (lin bus recessive, no regulator load, t < 60s) ( note 2 ) ..................... -0.3 to + 43v v bb battery voltage, transient iso 7637 test 1 ................................................................................... .................. -100v v bb battery voltage, transient iso 7637 test 2a .................................................................................. ...................+75v v bb battery voltage, transient iso 7637 test 3a .................................................................................. ................. -150v v bb battery voltage, transient iso 7637 test 3b .................................................................................. .................+100v v lbus bus voltage, continuous....................................................................................................... .............. -18 to + 30v v lbus bus voltage, transient ( note 3 ) .......................................................................................................... -27 to + 43v i lbus bus short-circuit current limit ............................................................................................... .....................200 ma esd protection on lin, v bb (iec 61000-4-2) ( note 4 ) ......................................................................................... 15 kv esd protection on lin, v bb (human body model) ( note 5 ) ................................................................................... 8 kv esd protection on all other pins (human body model) ( note 5 ) ............................................................................ 4 kv esd protection on all pins (charge device model) ( note 6 ).................................................................................1500v esd protection on all pins (machine model) ( note 7 ).............................................................................................200v maximum junction temperature ................................................................................................... .......................... 150 ? c storage temperature............................................................................................................ ......................-65 to + 150 ? c note 1: lin 2.x compliant specification. 2: sae j2602-2 compliant specification. 3: iso 7637/1 load dump compliant (t < 500 ms). 4: according to iec 61000-4-2, 330 ohm, 150 pf and tranceiver emc test specifications [2] to [4] 5: according to aec-q100-002/jesd22-a114 6: according to aec-q100-011b 7: according to aec-q100-003/jesd22-a115 2.2 nomenclature used in this document some terms and names used in this data sheet deviate from those referred to in the lin specifications. equivalent values are shown below. ? notice : stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. lin 2.1 name term used in the following tables definition v bat not used ecu operating voltage v sup v bb supply voltage at device pin v bus _ lim i sc current limit of driver v busrec v ih (l bus ) recessive state v busdom v il (l bus ) dominant state
? 2012-2014 microchip technology inc. ds20002299c-page 19 mcp2050 2.3 dc specifications dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bb = 6.0v to 18.0v, t a = -40c to +125c c reg = 10 f parameter sym. min. typ. max. units conditions power v bb quiescent operating current i bbq ? ? 200 a i out = 0 ma, l bus recessive v reg = 5.0v ? ? 200 a i out = 0 ma, l bus recessive v reg = 3.3v v bb quiescent operating current with watchdog enabled i bbq wdt ? ? 250 a i out = 0 ma, l bus recessive v reg = 5.0v 250 i out = 0 ma, l bus recessive v reg = 3.3v v bb ready current i bbrd ? ? 100 a i out = 0 ma, l bus recessive v reg = 5.0v ? ? 100 a i out = 0 ma, l bus recessive v reg = 3.3v v bb ready current wwdt enabled i bbrdwdt ? ? 150 a with voltage regulator on, transmitter off, receiver on, fault /t xe = v il , cs = v ih ,v reg = 5.0v 150 with voltage regulator on, transmitter off, receiver on, fault /t xe = v il , cs = v ih ,v reg = 3.3v v bb transmitter-off current with watchdog disabled i bbto ? ? 100 a with voltage regulator on, transmitter off, receiver on, fault /t xe = v il , cs = v ih ,v reg = 5.0v ? ? 100 a with voltage regulator on, transmitter off, receiver on, fault /t xe = v il , cs = v ih ,v reg = 3.3v v bb power-down current i bbpd ? 4.5 8 a with voltage regulator powered-off, receiver on and transmitter off, fault /t xe = v ih , t xd = v ih , cs = v il ) v bb current with v ss floating i bbnognd -1 ? 1mav bb = 12v, gnd to v bb , v lin = 0-18v note 1: internal current limited. 2.0 ms maximum recovery time (r lbus = 0 ? , t x = 0 , v lbus = v bb ). 2: characterized, not 100% tested. 3: in power-down mode, normal lin recessive/dominant threshold is disabled; v wk ( lbus ) is used to detect bus activities.
mcp2050 ds20002299c-page 20 ? 2012-2014 microchip technology inc. microcontroller interface high-level input voltage (t xd , fault /t xe , wwdttrig ) v ih 2.0 ? v reg +0.3 v low-level input voltage (t xd , fault /t xe , wwdttrig ) v i l -0.3 ? 0.8 v high-level input current (t xd , fault /t xe , wwdttrig ) i ih -2.5 ? 0.4 a input voltage = 4.0v. ~800 k ? internal adaptive pull-up low-level input current (t xd , fault /t xe , wwdttrig ) i il -10 ? ? a input voltage = 0.5v. ~800 k ? internal adaptive pull-up high-level input voltage (cs/lwake) v ih 2.0 ? v bb v through a current-limiting resistor low-level input voltage (cs/lwake) v il -0.3 ? 0.8 v high-level input current (cs/lwake) i ih ?? 8.0 a input voltage = 0.8v reg ~1.3 m ? internal pull- down to v ss low-level input current (cs/lwake) i il ?? 5.0 a input voltage = 0.2v reg ~1.3 m ? internal pull- down to v ss low-level output voltage (r xd ) v ol rxd ??0.2v reg vi ol = 2 ma high-level output voltage (r xd ) v oh rxd 0.8v reg ?? vi oh = 2 ma low-level output voltage (fault /t xe ) v olod ?1.0vi ol = 4 ma low-level output voltage (reset ) v olrst ??1.0v i ol = 4 ma 2.3 dc specifications (continued) dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bb = 6.0v to 18.0v, t a = -40c to +125c c reg = 10 f parameter sym. min. typ. max. units conditions note 1: internal current limited. 2.0 ms maximum recovery time (r lbus = 0 ? , t x = 0 , v lbus = v bb ). 2: characterized, not 100% tested. 3: in power-down mode, normal lin recessive/dominant threshold is disabled; v wk ( lbus ) is used to detect bus activities.
? 2012-2014 microchip technology inc. ds20002299c-page 21 mcp2050 bus interface high-level input voltage v ih (l bus )0.6 v bb ? ? v recessive state low-level input voltage v il (l bus )-8 ?0.4 v bb v dominant state input hysteresis v hys ? ? 0.175 v bb vv ih (l bus ) ? v il (l bus ) low-level output current i ol (l bus ) 40 ? 200 ma output voltage = 0.1 v bb , v bb = 12v pull-up current on input i pu (l bus )-180 ? -72 a~30k ? internal pull-up @ v ih (l bus ) = 0.7 v bb , v bb =12v short-circuit current limit i sc 50 ? 200 ma ( note 1 ) high-level output voltage v oh (l bus )0.8 v bb ?v bb v driver dominant voltage v_ losup ??1.1vv bb = 7.3v, r load = 1000 ? driver dominant voltage v_ hisup ??1.2vv bb = 18v, r load = 1000 ? input leakage current (at the receiver during dominant bus level) i bus _ pas _ dom -1 ? ? ma driver off, v bus = 0v, v bb = 12v input leakage current (at the receiver during recessive bus level) i bus _ pas _ rec -20 ? 20 a driver off, 8v < v bb < 18v 8v < v bu s < 18v v bus ? v bb leakage current (disconnected from ground) i bus _ no _ g nd -10 ? +10 a gnd device = v bb , 0v < v bus < 18v, v bb = 12v leakage current (disconnected from v bb ) i bus _no_p wr -10 ? +10 a v bb = gnd, 0 < v bus < 18v receiver center voltage v bus _ cnt 0.475 v bb 0.5 v bb 0.525 v bb vv bus _ cnt = (v il (l bus ) + v ih (l bus ))/2 slave termination r slave 20 30 47 k ? ( note 2 ) capacitance of slave node c slave 50 pf ( note 2 ) wake-up voltage threshold on lin bus v wk(lbus) ? ? 3.4 v wake up from power- down mode ( note 3 ) 2.3 dc specifications (continued) dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bb = 6.0v to 18.0v, t a = -40c to +125c c reg = 10 f parameter sym. min. typ. max. units conditions note 1: internal current limited. 2.0 ms maximum recovery time (r lbus = 0 ? , t x = 0 , v lbus = v bb ). 2: characterized, not 100% tested. 3: in power-down mode, normal lin recessive/dominant threshold is disabled; v wk ( lbus ) is used to detect bus activities.
mcp2050 ds20002299c-page 22 ? 2012-2014 microchip technology inc. voltage regulator ? 5.0v output voltage range v reg 4.85 5.00 5.15 v 0 ma < i out < 70 ma line regulation ? v out 1 ? 10 50 mv i out = 1 ma, 6.0v < v bb < 18v load regulation ? v out 2 ? 10 50 mv 5 ma < i out <70 ma 6.0v < v bb < 12v power supply ripple reject psrr ? ? 50 db 1 v pp @10-20 khz i load = 20 ma output noise voltage en ? ? 100 v rms 10 hz ? 40 mhz c filter = 10 f, c bp = 0.1 f, i load = 20 ma shutdown voltage threshold v sd 3.5 ? 4.0 v see figure 1-10 ( note 2 ) input voltage to turn off output v off 3.9 ? 4.5 v input voltage to turn on output v on 5.25 ? 6.0 v voltage regulator ? 3.3v output voltage v reg 3.20 3.30 3.40 v 0 ma < i out < 70 ma line regulation ? v out 1 ? 10 50 mv i out = 1 ma, 6.0v < v bb < 18v load regulation ? v out 2 ? 10 50 mv 5 ma < i out < 70 ma, 6.0v < v bb < 12v power supply ripple reject psrr ? ? 50 db 1 v pp @10-20 khz, i load = 20 ma output noise voltage en ? ? 100 v rms / ? hz 10 hz ? 40 mhz c filter = 10 f, c bp = 0.1 f, i load = 20 ma shutdown voltage v sd 2.5 ? 2.7 v see figure 1-10 ( note 2 ) 2.3 dc specifications (continued) dc specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v bb = 6.0v to 18.0v, t a = -40c to +125c c reg = 10 f parameter sym. min. typ. max. units conditions note 1: internal current limited. 2.0 ms maximum recovery time (r lbus = 0 ? , t x = 0 , v lbus = v bb ). 2: characterized, not 100% tested. 3: in power-down mode, normal lin recessive/dominant threshold is disabled; v wk ( lbus ) is used to detect bus activities.
? 2012-2014 microchip technology inc. ds20002299c-page 23 mcp2050 figure 2-1: esr curves fo r load capacitor selection load capacitor [uf] esr curves esr [ohm] 10 1 0.1 0.01 0.001 10 100 1000 1 0.1 instable instable instable stable only with tantalum or electrolytic cap. stable with tantalum, electrolytic and ceramic cap. u nstable u nstable u nstable load capacitance note 1 the graph shows the minimum capacitance after de-rating due to tolerance, temperature and voltage
mcp2050 ds20002299c-page 24 ? 2012-2014 microchip technology inc. 2.4 ac specifications ac characteristics electrical characteristics : unless otherwise indicated, all limits are specified for v bb = 6.0v to 18.0v; t a = -40c to +125c parameter sym. min. typ. max. units test conditions bus interface - constant slope time parameters (dc specifications are for a v bb range of 6.0 to 18.0v) slope rising and falling edges t slope 3.5 ? 22.5 s 7.3v <= v bb <= 18v propagation delay of transmitter t transpd ??5.0st transpd = max (t transpdr or t transpdf ) propagation delay of receiver t recpd ??6.0st recpd = max (t recpdr or t recpdf ) symmetry of propagation delay of receiver rising edge w.r.t. falling edge t recsym -2.0 ? 2.0 s trecsym = max (t recpdf ? t recpdr ) r rxd 2.4 k ? ? to v cc , c rxd 20pf symmetry of propagation delay of transmitter rising edge w.r.t. falling edge t transsym -2.0 ? 2.0 s t transsym = max (t transpdf - t transpdr ) bus dominant time-out time t to(lin) ?25?ms time to sample of f ault /t xe for bus conflict reporting t fault ??32.5st fault = max (t transpd + t slope + t recpd ) duty cycle 1 @ 20.0 kbit/sec 0.396 ? ? %t bit c bus ;r bus conditions: 1nf; 1k ? | 6.8 nf; 660 ? | 10 nf; 500 ? th rec ( max ) = 0.744 x v bb , th dom ( max ) = 0.581 x v bb , v bb =7.0v - 18v; t bit = 50 s. d1 = t bus _ rec ( min ) / 2 x t bit ) duty cycle 2 @ 20.0 kbit/sec ? ? 0.581 %t bit c bus ;r bus conditions: 1nf; 1k ? | 6.8 nf; 660 ? | 10 nf; 500 ? th rec ( max ) = 0.284 x v bb , th dom ( max ) = 0.422 x v bb , v bb =7.6v - 18v; t bit = 50 s. d2 = t bus _ rec ( max ) / 2 x t bit ) duty cycle 3 @ 10.4 kbit/sec 0.417 ? ? %t bit c bus ;r bus conditions: 1nf; 1k ? | 6.8 nf; 660 ? | 10 nf; 500 ? th rec ( max ) = 0.778 x v bb , th dom ( max ) = 0.616 x v bb , v bb =7.0v - 18v; t bit = 96 s. d3 = t bus _ rec ( min ) / 2 x t bit ) duty cycle 4 @ 10.4 kbit/sec ? ? 0.590 %t bit c bus ;r bus conditions: 1nf; 1k ? | 6.8 nf; 660 ? | 10 nf; 500 ? th rec ( max ) = 0.251 x v bb , th dom ( max ) = 0.389 x v bb , v bb =7.6v - 18v; t bit = 96 s. d4 = t bus _ rec ( max ) / 2 x t bit )
? 2012-2014 microchip technology inc. ds20002299c-page 25 mcp2050 2.5 thermal specifications voltage regulator bus activity debounce time t bdb 30 80 250 s bus activity to voltage regulator enabled t bactive 35 ? 200 s voltage regulator enabled to ready t vevr 300 ? 1200 s ( note 1 ) chip select to ready mode t csr ??230s chip select to power-down t cspd ? ? 300 s ( note 2 ) short-circuit to shutdown t shutdown 20 ? 100 s reset timing v reg ok detect to reset inactive t rpu ??60.0s v reg not ok detect to reset active t rpd ??60.0s wwdt reset pulse length t wdrst ? 150 ? s -40/+100% power-up watchdog window length t powerup ?27.2?ms 15% rwwdtselect = 33 k ? ( note 2 , note 3 ) watchdog window length t wlength 5.95 7 8.05 ms 15% rwwdtselect = 33 k ? ( note 4 , note 5 ) 102 120 138 ms 15% rwwdtselect = 680 k ? ( note 4 , note 5 ) note 1: time depends on external capacitance and load. test condition: c reg = 4.7uf, no resistor load. 2: characterized, not 100% tested. 3: t powerup = 0.8 ms (rwwdtselect+1); r in k ? . 4: t wlength = (0.175 ms rwwdtselect) + 1.2 15%; r in k ? . 5: characterized; tested for rwwdtselect = 33 k ? and 680 k ? parameter symbol typ max units test conditions recovery temperature ? recovery +140 ? ? c shutdown temperature ? shutdown +150 ? ? c short circuit recovery time t therm 1.5 5.0 ms thermal package resistances thermal resistance, 14l-pdip ? ja 70 ? ? c/w thermal resistance, 14l-soic ? ja 90.8 ? ? c/w thermal resistance, 20l-qfn ? ja 44.6 ? ? c/w note 1: the maximum power dissipation is a function of t jmax , ? ja and ambient temperature t a . the maximum allowable power dissipation at an ambient temperature is p d = (t jmax - t a ) ?? ja . if this dissipation is exceeded, the die temperature will rise above 150 ? c and the mcp2050 will go into thermal shutdown. 2.4 ac specifications (continued) ac characteristics electrical characteristics : unless otherwise indicated, all limits are specified for v bb = 6.0v to 18.0v; t a = -40c to +125c parameter sym. min. typ. max. units test conditions
mcp2050 ds20002299c-page 26 ? 2012-2014 microchip technology inc. 2.6 typical performance curves note: unless otherwise indicated, v bb = 6.0v to 18.0v; t a = -40c to +125c figure 2-2: typical i bbq vs. temperature ? 5.0v. figure 2-3: typical i bbto vs. temperature ? 5.0v. figure 2-4: typical i pd vs. temperature ? 5.0v. figure 2-5: typical i bbq vs. temperature ? 3.3v. figure 2-6: typical i bbto vs. temperature ? 3.3v. figure 2-7: typical i pd vs. temperature ? 3.3v. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 80 100 120 140 160 180 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 ibbq (a) temperature( c) v bb = 6v v bb = 12v v bb = 18v 50 60 70 80 90 -40 -25 -10 5 20 35 50 65 80 95 110 125 ibbto (a) temperature( c) v bb = 6v v bb = 12v v bb = 18v 4 4.2 4.4 4.6 4.8 5 5.2 -40 -25 -10 5 20 35 50 65 80 95 110 125 ipd (a) temperature( c) v bb = 6v v bb = 12v v bb = 18v 80 100 120 140 160 180 200 -40 -25 -10 5 20 35 50 65 80 95 110 125 ibbq (a) temperature( c) v bb = 6v v bb = 12v v bb = 18v 50 60 70 80 90 100 -40 -25 -10 5 20 35 50 65 80 95 110 125 ibbto (a) temperature( c) v bb = 6v v bb = 12v v bb = 18v 4 4.2 4.4 4.6 4.8 5 5.2 -40 -25 -10 5 20 35 50 65 80 95 110 125 ipd (a) temperature( c) v bb =6v v bb =12v v bb =18v
? 2012-2014 microchip technology inc. ds20002299c-page 27 mcp2050 figure 2-8: 5.0 v reg vs. i reg at v bb = 12v. figure 2-9: 3.3v v reg vs. i reg at v bb = 12v. 0 1 2 3 4 5 6 0 50 100 150 200 250 300 v reg (v) i reg (ma) -40c +25c +90c +125c 0 0.5 1 1.5 2 2.5 3 3.5 0 50 100 150 200 250 300 v reg (v) i reg (ma) -40c +25c +90c +125c
mcp2050 ds20002299c-page 28 ? 2012-2014 microchip technology inc. 2.7 timing diagrams and specifications figure 2-10: bus timing diagram figure 2-11: regulator bus wake timing diagram .95v lbus .05v lbus t transpdr t recpdr t transpdf t recpdf t xd l bus r xd internal t xd /r xd compare fault sampling t fault t fault fault /t xe output stable stable stable match match match match match hold value hold value 50% 50% .50v bb 50% 50% 0.0v v reg l bus v wk(lbus) t vevr v reg-nom t bdb t bactive
? 2012-2014 microchip technology inc. ds20002299c-page 29 mcp2050 figure 2-12: cs/lwake, regulator and reset timing diagram t cspd t csr cs/lwake v reg v reg-nom reset t rpu t vevr t rpd
mcp2050 ds20002299c-page 30 ? 2012-2014 microchip technology inc. 3.0 packaging information 3.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 14-lead soic (.150?) example mcp2050 -500 e/sl ^^ 1429256 3 e 14-lead pdip (300 mil) example mcp2050 -500 e/p ^^ 1429256 3 e 20-lead qfn (5x5x0.9 mm) example pin 1 pin 1 mcp2050 500e/mq ^^ 1429256 3 e
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mcp2050 ds20002299c-page 32 ? 2012-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012-2014 microchip technology inc. ds20002299c-page 33 mcp2050 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
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? 2012-2014 microchip technology inc. ds20002299c-page 35 mcp2050 20-lead plastic quad flat, no lead package (mq) C 5x5x0.9 mm body [qfn] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging microchip technology drawing c04-120a
mcp2050 ds20002299c-page 36 ? 2012-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012-2014 microchip technology inc. ds20002299c-page 37 mcp2050 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . device: mcp2050: lin transceiver with voltage regulator mcp2050t: lin transceiver with voltage regulator (tape and reel) (soic and qfn) tape and reel option: blank = standard packaging (tube or tray) t = tape and reel (1) temperature range: e = -40c to +125c package: mq = 20-lead plastic quad flat, no lead package ? 5x5x0.9 mm body (qfn) p = 14-lead plastic dual in-line ? 300 mil body (pdip) sl = 14-lead plastic small outline ? narrow, 3.90 mm body (soic) part no. ?x /xx package temperature range device examples: a) mcp2050-330e/p: 3.3v, extended temperature, 14-ld pdip package b) mcp2050-330e/mq: 3.3v, extended temperature, 20-ld qfn package c) mcp2050t-330e/mq: tape and reel, 3.3v, extended temperature, 20-ld qfn package d) mcp2050-330e/sl: 3.3v, extended temperature, 14-ld soic package e) mcp2050t-330e/sl: tape and reel, 3.3v, extended temperature, 14-ld soic package f) mcp2050-500e/p: 5.0v, extended tempera- ture, 14-ld pdip package g) mcp2050-500e/mq: 5.0v, extended tempera- ture, 20-ld qfn package h) mcp2050t-500e/mq: tape and reel, 5.0v, extended temperature, 20-ld qfn package i) mcp2050-500e/sl: 5.0v, extended tempera- ture, 14-ld soic package j) mcp2050t-500e/sl: tape and reel, 5.0v, extended temperature, 14-ld soic package [x] (1) tape and reel option note 1: tape and reel identifier only appears in the catalog part number description. this identi- fier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option.
mcp2050 ds20002299c-page 38 ? 2012-2014 microchip technology inc. appendix a: revision history revision d (september 2014) the following is the list of modifications: 1. added exposed thermal pad pin on qfn and in section 1.3, pin descriptions . 2. updated figure 1-7 . 3. added note in figure 2-1 . 4. added ac parameter for wwdt in section 2.4, ac specifications . 5. created new section 2.6, typical perfor- mance curves . 6. fixed minor typographical errors. revision c (august 2012) the following is the list of modifications: 1. removed two notes in section 2.4 ?ac speci- fications? . revision b (april 2012) the following is the list of modifications: 1. corrected a label in figure 1-12 . 2. corrected a label in figure 1-13 . 3. updated the product identification system page. revision a (march 2012) original release of this document.
? 2012-2014 microchip technology inc. ds20002299c-page 39 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2012-2014, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63276-639-7 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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